Multi-processor systems, such as servers and telecommunication (Telco) systems, for example, use input output (IO) subsystems to connect and communicate the host multi-processor system with external communicating units. Around 1992, the industry established an industry standards group, referred to as the Peripheral Component Interconnect—Special Interest Group (PCI-SIG), which was chartered with the development and management of a PCI bus specification as an industry standard for a high-performance IO interconnect to transfer data between one or more central processing units (CPUs) of the host system and the associated peripherals. Recently, the PCI-SIG introduced a successor to PCI called PCI Express (PCI-E) which is emerging as the industry standard IO subsystems interconnect technology for processor systems from small handheld computers, to desktops, small servers, and large SMP servers and mainframes.
The PCI-E standard includes the form factors, connectivity, signal level, and the like for enclosures and IO option cards. Examples of typical IO option cards include network interface cards, such as Ethernet, hard disk storage controller cards such as SCSI and SAS, cluster interconnect cards such as Infiniband™, and the like. One of the new PCI-E form factor technology standards is the PCI-E Server IO Modules (SIOMs). Generally, large SMP IO subsystems implementing the PCI-E SIOM standard are built using an IO motherboard configuration which comprises an enclosure or box having a motherboard and a plurality of module slots for accepting a plurality of SIOMs. Each SIOM includes a standardized connector for connecting electrically to a small “Riser board” and then to the motherboard. The motherboard includes etched conductive runs and one or more IO controller integrated circuits (ICs) containing a plurality of PCI-E Root Ports for interconnecting the SIOMs with the host multi-processor system. The IO enclosures are generally mounted in racks of a cabinet which also houses the multi-processor system and interconnecting IO interface wiring cables.
The PCI-E standard provides for Root Port IO controllers, generally in the form of integrated circuits or chips, to control the communication among the multi-processor system, the SIOMs and the external communicating units. Currently, these IO controller chips are fixedly disposed or integrated on the motherboard, rendering the motherboard active. Thus, while a standard enclosure allows for replaceable SIOMs, it does not permit easy replacement of the IO controller chips of the backplane motherboard for different applications. In addition, the IO operational or slot speeds and link widths are dedicated.
Multi-processor computer systems that may range from four central processing unit (CPU) enclosure types to sixty-four CPU mainframes generally use unique physical implementations of IO enclosures along with different active motherboards to meet the needs of the various applications. This becomes problematic because of the cost of manufacturing, upgrading, and maintaining the many different physical entities and models residing in the field at customer sites. In addition, to support future technology and slot speed upgrades, the entire IO subassembly including the active motherboard needs to be replaced. Moreover, the current IO enclosure implementations do not permit the option to use different cable technologies for the external interface interconnections to support future interconnect upgrades and performance options.